Sr. ASIC Design Engineer - Switch Design | Cornelis Networks | Remote

**Overview**

Join Cornelis Networks, the leader in high-performance scale-out networking for AI and HPC datacenters. We're seeking a Senior ASIC Design Engineer to architect next-generation switch solutions that power breakthrough computational workloads. As part of our globally distributed team spanning multiple countries, you'll help build world-class SoCs for high-performance computing and artificial intelligence applications.

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Responsibilities **

• Architect and develop core elements of cutting-edge Ethernet switch ASICs with emphasis on RTL implementation and latency enhancement • Create microarchitecture specifications for high-velocity packet processing subsystems handling transmit/receive operations • Build RTL implementations using Verilog/System Verilog for minimal-latency data pathways, encompassing Network-on-Chip (NoC) and crossbar architectures • Establish timing parameters for RTL modules while partnering with Physical Design teams for timing closure optimization • Collaborate with verification teams to develop comprehensive test strategies covering block and system-level validation • Provide post-silicon support by working across hardware, firmware, and software teams to troubleshoot ASIC challenges • Drive performance enhancement initiatives and power-conscious design approaches for switch subsystems

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Requirements **

• Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or equivalent discipline • 10+ years of professional digital design experience with strong Verilog and System Verilog skills • Deep understanding of Ethernet frameworks and networking protocol stacks • Hands-on experience with NoC architectures, crossbar implementations, or Ethernet switch ASIC development and system debugging • Proven track record in RTL design for high-speed or ultra-low-latency ASIC subsystems • Working knowledge of timing closure processes and contemporary physical design approaches • Demonstrated expertise in system-level troubleshooting and analysis

Monday to Friday, 9 AM – 5 PM (full-time)